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preliminary cy14b104l, cy14b104n 4 mbit (512k x 8/256k x 16) nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-07102 rev. *i revised june 20, 2008 features 15 ns, 20 ns, 25 ns, and 45 ns access times internally organized as 512k x 8 (cy14b104l) or 256k x 16 (cy14b104n) hands off automatic store on power down with only a small capacitor store to quantumtrap ? nonvolatile elements initiated by software, device pin, or autostore ? on power down recall to sram initiated by software or power up infinite read, write, and recall cycles 200,000 store cycles to quantumtrap 20 year data retention single 3v +20%, ?10% operation commercial and industrial temperatures 48-pin fbga and 44/54-pin tsop - ii packages pb-free and rohs compliance functional description the cypress cy14b104l/cy14b104n is a fast static ram, with a nonvolatile element in each memory cell. the memory is organized as 512k words of 8 bits each or 256k words of 16 bits each. the embedded nonvolatile elements incorporate quantumtrap technology, producing the world?s most reliable nonvolatile memory. the sram provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. a 0 - a 18 address we oe ce v cc v ss v cap dq0 - dq7 hsb cy14b104l bhe ble logic block diagram [1] [1] cy14b104n note 1. address a 0 - a 18 and data dq0 - dq7 for x8 configuration, address a 0 - a 17 and data dq0 - dq15 for x16 configuration. [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 2 of 23 pinouts figure 1. pin diagram - 48 fbga figure 2. pin diagram - 44 tsop ii we v cc a 11 a 10 v cap a 6 a 0 a 3 ce nc nc dq0 a 4 a 5 nc dq2 dq3 nc v ss a 9 a 8 oe v ss a 7 nc nc nc a 17 a 2 a 1 nc v cc dq4 nc dq5 dq6 nc dq7 nc a 15 a 14 a 13 a 12 hsb 3 2 6 5 4 1 d e b a c f g h a 16 a 18 nc dq1 48-fbga (not to scale) top view (x8) [2] [3] we v cc a 11 a 10 v cap a 6 a 0 a 3 ce dq10 dq8 dq9 a 4 a 5 dq13 dq12 dq14 dq15 v ss a 9 a 8 oe v ss a 7 dq0 bhe nc a 17 a 2 a 1 ble v cc dq2 dq1 dq3 dq4 dq5 dq6 dq7 a 15 a 14 a 13 a 12 hsb 3 2 6 5 4 1 d e b a c f g h a 16 nc nc dq11 48-fbga (not to scale) top view (x16) [2] [3] notes 2. address expansion for 8 mbit. nc pin not connected to die. 3. address expansion for 16 mbit. nc pin not connected to die. v ss dq6 dq5 dq4 v cc a 13 dq3 a 12 dq2 dq1 dq0 ble a 9 ce a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 11 a 10 a 14 bhe oe a 15 a 16 a 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii top view (not to scale) we dq7 a 0 v ss v cc dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 v cap (x16) nc a 8 nc nc v ss dq6 dq5 dq4 v cc a 13 dq3 a 12 dq2 dq1 dq0 oe a 9 ce nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 11 a 7 a 14 a 15 a 16 a 17 a 18 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44 - tsop ii top view (not to scale) a 10 nc we dq7 hsb nc v ss v cc v cap nc (x8) [2] [3] [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 3 of 23 figure 3. pin diagram - 54 pin tsop ii (x16) pin definitions pin name io type description a 0 ? a 18 input address inputs used to select one of the 524, 288 bytes of the nvsram for x8 configuration . a 0 ? a 17 address inputs used to select one of the 262,144 bytes of the nvsram for x16 configuration . dq0 ? dq7 input/output bidirectional data io lines for x8 configuration . used as input or output lines depending on operation. dq0 ? dq15 bidirectional data io lines for x16 configuration . used as input or output lines depending on operation. we input write enable input, active low . when selected low, data on the io pins is written to the address location latched by the falling edge of ce . ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. io pins are tri-stated on deasserting oe high. bhe input byte high enable, active low . controls dq15 - dq8. ble input byte low enable, active low . controls dq7 - dq0. v ss ground ground for the device . must be connected to the ground of the system. v cc power supply power supply inputs to the device . hsb input/output hardware store busy (hsb) . when low this output indicates that a hardware store is in progress. when pulled low external to the chip it initiates a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional). v cap power supply autostore capacitor . supplies power to the nvsram during power loss to store data from sram to nonvolatile elements. nc no connect no connect . do not connect this pin to the die. pinouts (continued) a 17 dq7 dq6 dq5 dq4 v cc dq3 dq2 dq1 dq0 nc a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 v cap we a 8 a 10 a 11 a 12 a 13 a 14 a 15 a 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 54 - tsop ii top view ( not to scale) oe ce v cc nc v ss nc a 9 nc nc nc nc nc nc 54 53 52 51 49 50 hsb bhe ble dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 (x16) [2] [3] [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 4 of 23 device operation the cy14b104l/cy14b104n nvsram is made up of two functional components paired in the same physical cell. they are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to the sram (the recall operation). using this unique arch itecture, all cells are stored and recalled in parallel. during the store and recall operations, sram read and write operations are inhibited. the cy14b104l/cy14b104n supports infinite reads and writes similar to a typical sram. in addition, it provides infinite recall operations from the nonvolatile cells and up to 200k store operations. sram read the cy14b104l/cy14b 104n performs a read cycle when ce and oe are low and we and hsb are high. the address specified on pins a 0-18 or a 0-17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each are accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle #1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle #2). the data output repeatedly responds to address changes within the t aa access time without the need for transi- tions on any control input pins. this remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed when ce and we are low and hsb is high. the address inputs must be stable before entering the write cycle and must re main stable until ce or we goes high at the end of the cycle. the data on the common io pins dq 0?15 are written into the memory if the data is valid t sd before the end of a we controlled write or bef ore the end of an ce controlled write. it is recommended that oe be kept high during the entire write cycle to avoid data bus contention on common io lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the cy14b104l/cy14b104n stores data to the nvsram using one of the following three storage operations: hardware store activated by hsb; software store activated by an address sequence; autostore on device power down. the autostore operation is a unique feature of quantumtrap technology and is enabled by default on the cy14b104l/cy14b104n. during a normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 4 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to dc electrical characteristics on page 7 for the size of v cap . to reduce unnecessary nonvolatile stores, autostore and hardware store operations are ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiat ed store cycles are performed regardless of whether a write operation has taken place. the hsb signal is monitored by the syst em to detect if an autostore cycle is in progress. figure 4. autostore mode hardware store operation the cy14b104l/cy14b104n provides the hsb pin to control and acknowledge the store operations. use the hsb pin to request a hardware store cycle. when the hsb pin is driven low, the cy14b104l/cy14b104n conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram has taken place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the cy14b104l/cy14b104n continues sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it is allowed a time, t delay to complete. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. during any store operation, regardless of how it is initiated, the cy14b104l/cy14b104n continues to drive the hsb pin low,releasing it only when the store is complete.upon completion of the store operation, the cy14b104l/cy14b104n remains disabled until the hsb pin returns high. leave the hsb unconnected if it is not used. 0.1uf vcc 10kohm v cap vcc we v cap v ss [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 5 of 23 hardware recall (power up) during power up or after any low power condition (v cc preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 6 of 23 preventing autostore the autostore function is disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore is re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled, a manual store operation (hardware or software) must be issued to save the autostore state through su bsequent power down cycles. the part comes from the factory with autostore enabled. data protection the cy14b104l/cy14b104n protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc < v switch . if the cy14b104l/cy14b104n is in a write mode (both ce and we are low) at power up, after a recall or store, the write is inhibited until a negative transition on ce or we is detected. this protects against inadvertent writes during power up or brown out conditions. noise considerations refer cy application note an1064 . l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [4,5,6] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [4,5,6] table 1. mode selection (continued) ce we oe a15 - a0 mode io power [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 7 of 23 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied ............................................ ?55 c to +150 c supply voltage on v cc relative to gnd ..........?0.5v to 4.1v voltage applied to outputs in high-z state....................................... ?0.5v to v cc + 0.5v input voltage.............................................?0.5v to vcc+0.5v transient voltage (<20 ns) on any pin to ground potential .................. ?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount pb soldering temperature (3 seconds) .......................................... +260 c output short circuit current [7] .................................... 15 ma static discharge voltage....... ........... ............ ............ > 2001v (per mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v to 3.6v industrial ?40 c to +85 c 2.7v to 3.6v dc electrical characteristics over the operating range (v cc = 2.7v to 3.6v) [9] parameter description test conditions min max unit i cc1 average v cc current t rc = 15 ns t rc = 20 ns t rc = 25 ns t rc = 45 ns dependent on output loading and cycle rate.values obtained without output loads. i out = 0 ma commercial 70 65 65 50 ma ma ma industrial 75 70 70 52 ma ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max average current for duration t store 6ma i cc3 [8] average v cc current at t rc = 200 ns, 3v, 25c typical we > (v cc ? 0.2). all other i/p cycling. dependent on output loading and cycle rate. values obtained without output loads. 35 ma i cc4 average v cap current during autostore cycle all inputs don?t care, v cc = max average current for duration t store 6ma i sb v cc standby current ce > (v cc ? 0.2). all others v in < 0.2v or > (v cc ? 0.2v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0 mhz. 3ma i ix input leakage current (except hsb ) v cc = max, v ss < v in < v cc ?1 +1 a input leakage current (for hsb ) v cc = max, v ss < v in < v cc ?100 +1 a i oz off-state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih ?1 +1 a v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap storage capacitor between v cap pin and v ss , 5v rated 61 82 f notes 7. outputs shorted for no more than one second. only one output shorted at a time. 8. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperat ure), and v cc = 3v. not 100% tested. 9. the hsb pin has i out =-10 ua for v oh of 2.4v.this parameter is characterized but not tested. [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 8 of 23 ac test conditions input pulse levels ....................................................0v to 3v input rise and fall times (10% - 90%) ........................ <5 ns input and output timing reference levels .................... 1.5v capacitance in the following table, the capacitance parameters are listed. [10] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0v 7pf c out output capacitance 7 pf thermal resistance in the following table, the thermal resistance parameters are listed. [10] parameter description test conditions 48-fbga 44-tsop ii 54-tsop ii unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 28.82 31.11 30.73 c/w jc thermal resistance (junction to case) 7.84 5.56 6.08 c/w figure 5. ac test loads 3.0v output 5 pf r1 r2 789 3.0v output 30 pf r1 r2 789 for tri-state specs 577 577 10. these parameters are guaranteed but not tested. [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 9 of 23 ac switching characteristics parameters description 15 ns 20 ns 25 ns 45 ns unit cypress parameters alt parameters min max min max min max min max sram read cycle t ace t acs chip enable access time 15 20 25 45 ns t rc [11] t rc read cycle time 15 20 25 45 ns t aa [12] t aa address access time 15 20 25 45 ns t doe t oe output enable to data valid 10 10 12 20 ns t oha t oh output hold after address change 3333ns t lzce [13] t lz chip enable to output active 3 3 3 3 ns t hzce [13] t hz chip disable to output inactive 7 8 10 15 ns t lzoe [13] t olz output enable to output active 0 0 0 0 ns t hzoe [13] t ohz output disable to output inactive 7 8 10 15 ns t pu [10] t pa chip enable to power active 0 0 0 0 ns t pd [10] t ps chip disable to power standby 15 20 25 45 ns t dbe - byte enable to data valid 10 10 12 20 ns t lzbe - byte enable to output active 0 0 0 0 ns t hzbe - byte disable to output inactive 7 8 10 15 ns sram write cycle t wc t wc write cycle time 15 20 25 45 ns t pwe t wp write pulse width 10152030ns t sce t cw chip enable to end of write 15 15 20 30 ns t sd t dw data setup to end of write 5 8 10 15 ns t hd t dh data hold after end of write 0 0 0 0 ns t aw t aw address setup to end of write 10 15 20 30 ns t sa t as address setup to start of write 0 0 0 0 ns t ha t wr address hold after end of write 0000ns t hzwe [13,14] t wz write enable to output disable 7 8 10 15 ns t lzwe [13] t ow output active after end of write 3333ns t bw - byte enable to end of write 15 15 20 30 ns notes 11. we must be high during sram read cycles. 12. device is continuously selected with ce and oe both low. 13. measured 200 mv from steady state output voltage. 14. if we is low when ce goes low, the outputs remain in the high impedance state. [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 10 of 23 autostore/power up recall parameters description cy14b104l/cy14b104n unit min max t hrecall [15] power up recall duration 20 ms t store [16] store cycle duration 15 ms v switch low voltage trigger level 2.65 v t vccrise vcc rise time 150 s software controlled store/recall cycle in the following table, the software controlled store/recall cycle parameters are listed. [17, 18] parameters description 15 ns 20 ns 25 ns 45 ns unit min max min max min max min max t rc store/recall initiation cycle time 15 20 25 45 ns t as address setup time 0 0 0 0 ns t cw clock pulse width 12152030 ns t ghax address hold time 1 1 1 1 ns t recall recall duration 200 200 200 200 s t ss [19, 20] soft sequence processing time 70 70 70 70 s hardware store cycle parameters description cy14b104l/cy14b104n unit min max t delay [21] time allowed to comp lete sram cycle 1 70 s t hlhx hardware store pulse width 15 ns switching waveforms figure 6. sram read cycle #1: address controlled [11, 12, 22] t rc t aa t oha address dq (data out) data valid notes 15. t hrecall starts from the time v cc rises above v switch. 16. if an sram write has not tak en place since the last nonvolatil e cycle, no store takes place. 17. the software sequence is clocked with ce controlled or oe controlled reads. 18. the six consecutive addresses must be read in the order listed in table 1 on page 5. we must be high during all six consecutive cycles. 19. this is the amount of time it takes to take action on a soft sequence command.vcc power must remain high to effectively regi ster command. 20. commands such as store and recall lock out io until operation is complete which further increases this time. see the specifi c command 21. on a hardware store initiation, sram operation continues to be enabled for time t delay to allow read and write cycles to complete. 22. hsb must remain high during read and write cycles. [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 11 of 23 figure 7. sram read cycle #2: ce and oe controlled [11, 22, 24] figure 8. sram write cycle #1: we controlled [14, 22, 23, 24] switching waveforms (continued) address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe data valid active standby t pu dq (data out) icc t lzbe t dbe t hzbe hzoe t t hzce bhe , ble t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data bhe , ble t bw notes 23. ce or we must be > v ih during address transitions. 24. bhe and ble are applicable for x16 configuration only. [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 12 of 23 figure 9. sram write cycle #2: ce controlled [14, 22, 23, 24] figure 10. autostore or power up recall [25] note 25. read and write cycles are ignored during store, recall, and while vcc is below v switch. switching waveforms (continued) t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid bhe , ble t bw v cc v switch t store t store t hrecall t hrecall autostore power-up recall read & write inhibited store occurs only if a sram write has happened no store occurs without atleast one sram write t vccrise [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 13 of 23 figure 11. ce controlled software store/recall cycle [18] figure 12. oe controlled software store/recall cycle [18] switching waveforms (continued) t rc t rc address # 1 address # 6 address t as t cw t ghax t store / t recall data valid data valid high impedance ce oe dq (data) a a a a a a a a a a a a a a [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 14 of 23 figure 13. hardware store cycle [21] figure 14. soft sequence processing [19, 20] switching waveforms (continued) t ss t ss [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 15 of 23 ordering information speed (ns) ordering code package diagram package type operating range 15 cy14b104la-zs15xct 51-85087 44-pin tsop ii commercial cy14b104l-zs15xit 51-85087 44-pin tsop ii industrial cy14b104l-zs15xi 51-85087 44-pin tsop ii CY14B104L-BA15XCT 51-85128 48-ball fbga commercial cy14b104l-ba15xit 51-85128 48-ball fbga industrial cy14b104l-ba15xi 51-85128 48-ball fbga cy14b104l-zsp15xct 51-85160 54-pin tsop ii commercial cy14b104l-zsp15xit 51-85160 54-pin tsop ii industrial cy14b104l-zsp15xi 51-85160 54-pin tsop ii cy14b104n-zs15xct 51-85087 44-pin tsop ii commercial cy14b104n-zs15xit 51-85087 44-pin tsop ii industrial cy14b104n-zs15xi 51-85087 44-pin tsop ii cy14b104n-ba15xct 51-85128 48-ball fbga commercial cy14b104n-ba15xit 51-85128 48-ball fbga industrial cy14b104n-ba15xi 51-85128 48-ball fbga cy14b104n-zsp15xct 51-85160 54-pin tsop ii commercial cy14b104n-zsp15xit 51-85160 54-pin tsop ii industrial cy14b104n-zsp15xi 51-85160 54-pin tsop ii 20 cy14b104la-zs20xct 51-85087 44-pin tsop ii commercial cy14b104l-zs20xit 51-85087 44-pin tsop ii industrial cy14b104l-zs20xi 51-85087 44-pin tsop ii cy14b104l-ba20xct 51-85128 48-ball fbga commercial cy14b104l-ba20xit 51-85128 48-ball fbga industrial cy14b104l-ba20xi 51-85128 48-ball fbga cy14b104l-zsp20xct 51-85160 54-pin tsop ii commercial cy14b104l-zsp20xit 51-85160 54-pin tsop ii industrial cy14b104l-zsp20xi 51-85160 54-pin tsop ii cy14b104n-zs20xct 51-85087 44-pin tsop ii commercial cy14b104n-zs20xit 51-85087 44-pin tsop ii industrial cy14b104n-zs20xi 51-85087 44-pin tsop ii cy14b104n-ba20xct 51-85128 48-ball fbga commercial cy14b104n-ba20xit 51-85128 48-ball fbga industrial cy14b104n-ba20xi 51-85128 48-ball fbga cy14b104n-zsp20xct 51-85160 54-pin tsop ii commercial cy14b104n-zsp20xit 51-85160 54-pin tsop ii industrial cy14b104n-zsp20xi 51-85160 54-pin tsop ii [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 16 of 23 25 cy14b104l-zs25xct 51-85087 44-pin tsop ii commercial cy14b104l-zs25xit 51-85087 44-pin tsop ii industrial cy14b104l-zs25xi 51-85087 44-pin tsop ii cy14b104l-ba25xit 51-85128 48-ball fbga industrial cy14b104l-ba25xi 51-85128 48-ball fbga cy14b104n-ba25xct 51-85128 48-ball fbga commercial cy14b104l-zsp25xct 51-85160 54-pin tsop ii commercial cy14b104l-zsp25xit 51-85160 54-pin tsop ii industrial cy14b104l-zsp25xi 51-85160 54-pin tsop ii cy14b104n-zs25xct 51-85087 44-pin tsop ii commercial cy14b104n-zs25xit 51-85087 44-pin tsop ii industrial cy14b104n-zs25xi 51-85087 44-pin tsop ii cy14b104n-ba25xct 51-85128 48-ball fbga commercial cy14b104n-ba25xit 51-85128 48-ball fbga industrial cy14b104n-ba25xi 51-85128 48-ball fbga cy14b104n-zsp25xct 51-85160 54-pin tsop ii commercial cy14b104n-zsp25xit 51-85160 54-pin tsop ii industrial cy14b104n-zsp25xi 51-85160 54-pin tsop ii 45 cy14b104l-zs45xct 51-85087 44-pin tsop ii commercial cy14b104l-zs45xit 51-85087 44-pin tsop ii industrial cy14b104l-zs45xi 51-85087 44-pin tsop ii cy14b104l-ba45xct 51-85128 48-ball fbga commercial cy14b104l-ba45xit 51-85128 48-ball fbga industrial cy14b104l-ba45xi 51-85128 48-ball fbga cy14b104l-zsp45xct 51-85160 54-pin tsop ii commercial cy14b104l-zsp45xit 51-85160 54-pin tsop ii industrial cy14b104l-zsp45xi 51-85160 54-pin tsop ii cy14b104n-zs45xct 51-85087 44-pin tsop ii commercial cy14b104n-zs45xit 51-85087 44-pin tsop ii industrial cy14b104n-zs45xi 51-85087 44-pin tsop ii cy14b104n-ba45xct 51-85128 48-ball fbga commercial cy14b104n-ba45xit 51-85128 48-ball fbga industrial cy14b104n-ba45xi 51-85128 48-ball fbga cy14b104n-zsp45xct 51-85160 54-pin tsop ii commercial cy14b104n-zsp45xit 51-85160 54-pin tsop ii industrial cy14b104n-zsp45xi 51-85160 54-pin tsop ii all parts are pb-free. the above table contains preliminary info rmation. please contact your local cypress sales representative for availability of these parts. ordering information (continued) speed (ns) ordering code package diagram package type operating range [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 17 of 23 part numbering nomenclature option: t - tape & reel blank - std. speed: 20 - 20 ns 25 - 25 ns data bus: l - x8 n - x16 density: 104 - 4 mb voltage: b - 3.0v cypress cy 14 b 104 l - zs p 15 x c t nvsram 14 - auto store + software store + hardware store temperature: c - commercial (0 to 70c) i - industrial (?40 to 85c) pb-free package: ba - 48 fbga zs - tsop ii p - 54 pin blank - 44 pin 45 - 45 ns 15 - 15 ns [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 18 of 23 package diagrams figure 15. 44-pin tsop ii (51-85087) max min. dimension in mm (inch) 11.938 (0.470) plane seating pin 1 i.d. 44 1 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) ejector pin r g o k e a x s 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) base plane 0.10 (.004) 22 23 top view bottom view 51-85087-*a [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 19 of 23 figure 16. 48-ball fbga - 6 mm x 10 mm x 1.2 mm (51-85128) package diagrams (continued) a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.20 max c seating plane 0.530.05 0.25 c 0.15 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 10.000.10 a 10.000.10 6.000.10 b 1.875 2.625 0.36 51-85128-d [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 20 of 23 figure 17. 54-pin tsop ii (51-85160) package diagrams (continued) 51-85160-** [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 21 of 23 document history page document title: cy14b104l/cy14b104n 4 mbit (512k x 8/256k x 16) nvsram document number: 001-07102 rev. ecn no. submission date orig. of change description of change ** 431039 see ecn tup new data sheet *a 489096 see ecn tup removed 48 ssop package added 48 fbga and 54 tsopii packages updated part numbering nomenclature and ordering information added soft sequence processing time waveform *b 499597 see ecn pci removed 35 ns speed bin added 55 ns speed bin. updated ac table for the same changed ?unlimited? read/write to ?infinite? read/write features section: changed typical i cc at 200-ns cycle time to 8 ma changed store cycles from 500k to 200k cycles shaded commercial grade in operating range table modified icc/is specs 48 fbga package nomenclature changed from bw to bv modified part nomenclature table. changes reflected in ordering information table *c 517793 see ecn tup removed 55ns speed bin changed pinout for 44tsopii and 54tsopii packages changed i sb to 1ma changed i cc4 to 3ma changed v cap min to 35 f changed v ih max to vcc + 0.5v changed t store to 15ms changed t pwe to 10ns changed t sce to 15ns changed t sd to 5ns changed t aw to 10ns removed t hlbl added timing parameters for bhe and ble - t dbe , t lzbe , t hzbe , t bw removed min specification for vswitch changed t glax to 1ns added t delay max of 70us changed t ss specification from 70us min to 70us max *d 774001 see ecn uha changed the data sheet from advance information to preliminary 48 fbga package code changed from bv to ba removed 48 fbga package in x8 configuration in ordering information. changed t dbe to 10ns in 15ns part changed t hzbe in 15ns part to 7ns and in 25ns part to10ns changed t bw in 15ns part to 15ns and in 25ns part to 20ns changed t glax to t ghax changed the value of i cc3 to 25ma changed the value of t aw in 15ns part to15ns changed a 18 and a 19 pins in fbga pin configuration to nc *e 914220 see ecn uha included all the information for 45 ns part in this data sheet [+] feedback
preliminary cy14b104l, cy14b104n document #: 001-07102 rev. *i page 22 of 23 *f 1889928 see ecn vsutmp8/ aesa added footnotes 1, 2 and 3. updated logic block diagram added 48-fbga (x8) pin diagram changed 8mb address expansion pin from pin 43 to pin 42 for 44-tsop ii (x8). updated pin definitions table. corrected typo in v il min spec changed the value of i cc3 from 25ma to 13ma changed i sb value from 1ma to 2ma rearranging of footnotes. updated ordering information table *g 2267286 see ecn gvch/p yrs added bhe and ble information in pin definitions table updated figure 4 (autostore mode) updated footnote 6 changed i cc2 & i cc4 from 3 ma to 6 ma changed i cc3 from 13 ma to 15 ma changed vcap from 35uf min and 57uf max value to 54uf min and 82uf max value changed i sb from 2 ma to 3 ma added input leakage current (i ix ) for hsb in dc electrical characteristics table corrected typo in t dbe value from 22 ns to 20 ns for 45 ns part corrected typo in t hzbe value from 22 ns to 15 ns for 45 ns part corrected typo in t aw value from 15 ns to 10ns for 15 ns part changed t recall from 100 to 200 us added footnotes 9 and 25; reframed footnote 14 and 21 added footnote 14 to figure 7 (sram write cycle #1) *h 2483627 see ecn gvch/p yrs removed 8 ma typical i cc at 200 ns cycle time in feature section referenced footnote 8 to i cc3 in dc characteristics table changed i cc3 from 15 ma to 35 ma changed vcap minimum value from 54 uf to 61 uf changed t avav to t rc figure 11:changed t sa to t as and t sce to t cw document title: cy14b104l/cy14b104n 4 mbit (512k x 8/256k x 16) nvsram document number: 001-07102 rev. ecn no. submission date orig. of change description of change [+] feedback
document #: 001-07102 rev. *i revised june 20, 2008 page 23 of 23 autostore and quantumtrap are registered trademarks of simtek corporation. all products and company names mentioned in this doc ument are the trademarks of their respective holders. preliminary cy14b104l, cy14b104n ? cypress semiconductor corporation, 2006-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb *i 2519319 06/20/08 gvch/p yrs added 20 ns access speed in ?features? added i cc1 for t rc =20 ns for both industrial and commecial temperature grade updated thermal resistance table values fo r 48-fbga, 44-tsop ii and 54-tsop ii packages added ac switching characterist ics specs for 20 ns access speed added software controlled store/recall cycle specs for 20 ns access speed updated ordering information a nd part numbering nomenclature document title: cy14b104l/cy14b104n 4 mbit (512k x 8/256k x 16) nvsram document number: 001-07102 rev. ecn no. submission date orig. of change description of change [+] feedback

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